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PD -97140
IRFP4668PBF
HEXFET(R) Power MOSFET
Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits G Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free
D
VDSS RDS(on) typ.
200V 8.0m: max. 9.7m: 130A
S
ID
D
G
D
S
TO-247AC
G D S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current c Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery e Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw
Max.
130 92 520 520 3.5 30 57 -55 to + 175 300 10lbxin (1.1Nxm) 760 See Fig. 14, 15, 22a, 22b,
Units
A W W/C V V/ns C
Avalanche Characteristics
EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy d Avalanche Current c Repetitive Avalanche Energy f mJ A mJ
Thermal Resistance
Symbol
RJC RCS RJA
Parameter
Junction-to-Case j Case-to-Sink, Flat Greased Surface Junction-to-Ambient ij
Typ.
--- 0.24 ---
Max.
0.29 --- 40
Units
C/W
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1
9/8/08
IRFP4668PBF
Static @ TJ = 25C (unless otherwise specified)
Symbol
V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) IDSS IGSS RG
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance
Min. Typ. Max. Units
200 --- --- 3.0 --- --- --- --- --- --- 0.21 8.0 --- --- --- --- --- 1.0 --- --- 9.7 5.0 20 250 100 -100 ---
Conditions
V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 5mAc m VGS = 10V, ID = 81A f V VDS = VGS, ID = 250A A VDS = 200V, VGS = 0V VDS = 200V, VGS = 0V, TJ = 125C nA VGS = 20V VGS = -20V
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd)
Min. Typ. Max. Units
S nC
Conditions
VDS = 50V, ID = 81A ID = 81A VDS = 100V VGS = 10V f ID = 81A, VDS =0V, VGS = 10V VDD = 130V ID = 81A RG = 2.7 VGS = 10V f VGS = 0V VDS = 50V = 1.0MHz VGS = 0V, VDS = 0V to 160V h VGS = 0V, VDS = 0V to 160V g
150 --- --- --- 161 241 --- 54 --- --- 52 --- --- 109 --- Turn-On Delay Time --- 41 --- Rise Time --- 105 --- Turn-Off Delay Time --- 64 --- Fall Time --- 74 --- Input Capacitance --- 10720 --- Output Capacitance --- 810 --- Reverse Transfer Capacitance --- 160 --- Effective Output Capacitance (Energy Related)h --- 630 --- --- 790 --- Effective Output Capacitance (Time Related)g
ns
pF
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) c Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- 130 520 A
Conditions
MOSFET symbol showing the integral reverse
D
G S
--- --- 1.3 V --- 130 --- ns --- 155 --- --- 633 --- nC TJ = 125C --- 944 --- --- 8.7 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
p-n junction diode. TJ = 25C, IS = 81A, VGS = 0V f TJ = 25C VR = 100V, IF = 81A TJ = 125C di/dt = 100A/s f TJ = 25C
Notes: Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.23mH RG = 25, IAS = 81A, VGS =10V. Part not recommended for use above this value. ISD 81A, di/dt 520A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For recom R is measured at TJ approximately 90C.
Coss while VDS is rising from 0 to 80% VDSS. mended footprint and soldering techniques refer to application note #AN-994.
2
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IRFP4668PBF
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
ID, Drain-to-Source Current (A)
100
ID, Drain-to-Source Current (A)
10
BOTTOM
100
BOTTOM
1
60s PULSE WIDTH
Tj = 25C
10 4.5V
0.1 4.5V 0.01 0.1 1 10 100 1000 VDS, Drain-to-Source Voltage (V)
60s PULSE WIDTH
Tj = 175C 1 0.1 1 10 100 1000 VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
Fig 2. Typical Output Characteristics
3.5
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID, Drain-to-Source Current()
3.0 2.5 2.0 1.5 1.0 0.5 0.0
ID = 81A VGS = 10V
100
TJ = 175C
10
TJ = 25C
1
VDS = 50V
0.1 3.0 4.0 5.0 6.0
60s PULSE WIDTH
7.0 8.0 9.0
VGS, Gate-to-Source Voltage (V)
-60 -40 -20 0 20 40 60 80 100120140160180 TJ , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
16000
VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd
Fig 4. Normalized On-Resistance vs. Temperature
16
VGS, Gate-to-Source Voltage (V)
ID= 81A VDS = 160V VDS = 100V VDS = 40V
12000
C, Capacitance (pF)
12
Ciss 8000
8
4000 Coss 0 1 Crss 10 VDS , Drain-to-Source Voltage (V) 100
4
0 0 40 80 120 160 200 QG Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFP4668PBF
1000
10000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA LIMITED BY R DS (on)
ISD, Reverse Drain Current (A)
100
TJ = 175C
1000 100sec 100 10msec 10 1msec 1 Tc = 25C Tj = 175C Single Pulse 0.1 1 DC
10
TJ = 25C
1 VGS = 0V 0.1 0.0 0.5 1.0 1.5 VSD , Source-to-Drain Voltage (V)
0.1 10 100 1000 VDS , Drain-toSource Voltage (V)
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
140 120
Fig 8. Maximum Safe Operating Area
250 Id = 5mA 240 230 220 210 200 190 -60 -40 -20 0 20 40 60 80 100120140160180 TJ , Temperature ( C )
ID , Drain Current (A)
100 80 60 40 20 0 25 50 75 100 125 150 175
TC , CaseTemperature (C)
Fig 9. Maximum Drain Current vs. Case Temperature
EAS, Single Pulse Avalanche Energy (mJ)
14 12 10
Fig 10. Drain-to-Source Breakdown Voltage
2500
2000
ID 18A 24A BOTTOM 81A
TOP
Energy (J)
8 6 4 2 0 0 40 80 120 160 200
1500
1000
500
0 25 50 75 100 125 150 175
VDS, Drain-to-Source Voltage (V)
Starting TJ, Junction Temperature (C)
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
4
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IRFP4668PBF
1
Thermal Response ( Z thJC )
0.1
D = 0.50 0.20 0.10
0.01
0.05 0.02 0.01
J
R1 R1 J 1 2
R2 R2
R3 R3 C 3
Ri (C/W)
(sec)
1
2
3
Ci= i/Ri Ci= i/Ri
0.063359 0.000278 0.110878 0.005836 0.114838 0.053606
0.001
SINGLE PULSE ( THERMAL RESPONSE )
0.0001 1E-006 1E-005 0.0001 0.001 0.01
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.1 1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse)
0.01 0.05 0.10 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C.
1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
10
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
800
EAR , Avalanche Energy (mJ)
600
TOP Single Pulse BOTTOM 1% Duty Cycle ID = 81A
400
200
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 22a, 22b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
175
0 25 50 75 100 125 150
Starting TJ , Junction Temperature (C)
PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFP4668PBF
6.0
70
VGS(th) Gate threshold Voltage (V)
ID = 1.0A
5.0
ID = 1.0mA ID = 250A
60 50
4.0
IRRM - (A)
40 30 20 IF = 52A VR = 100V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
3.0
2.0
1.0
10 0
-75 -50 -25 0 25 50 75 100 125 150 175
0.0
TJ , Temperature ( C )
dif / dt - (A / s)
Fig 16. Threshold Voltage Vs. Temperature
70 60
Fig. 17 - Typical Recovery Current vs. dif/dt
5000
4000 50
QRR - (nC)
IRRM - (A)
40 30 20 10 0 IF = 81A VR = 100V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
3000
2000 IF = 52A VR = 100V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
1000
0
dif / dt - (A / s)
dif / dt - (A / s)
Fig. 18 - Typical Recovery Current vs. dif/dt
5000
Fig. 19 - Typical Stored Charge vs. dif/dt
4000
QRR - (nC)
3000
2000 IF = 81A VR = 100V TJ = 125C TJ = 25C 0 100 200 300 400 500 600 700 800 900 1000
1000
dif / dt - (A / s)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFP4668PBF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 22a. Unclamped Inductive Test Circuit
VDS VGS RG RD
Fig 22b. Unclamped Inductive Waveforms
VDS 90%
D.U.T.
+
- VDD
V10V GS
Pulse Width 1 s Duty Factor 0.1 %
10% VGS
td(on) tr t d(off) tf
Fig 23a. Switching Time Test Circuit
Current Regulator Same Type as D.U.T.
Fig 23b. Switching Time Waveforms
Id Vds Vgs
50K 12V .2F .3F
D.U.T. VGS
3mA
+ V - DS
Vgs(th)
IG
ID
Current Sampling Resistors
Qgs1 Qgs2
Qgd
Qgodr
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Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
7
IRFP4668PBF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
TO-247AC Part Marking Information
EXAMPLE: THIS IS AN IRFPE30 WIT H AS S EMBLY LOT CODE 5657 AS S EMBLED ON WW 35, 2001 IN T HE AS S EMBLY LINE "H" Note: "P" in ass embly line pos ition indicates "Lead-Free" INTERNATIONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER
IRFPE30
56 135H 57
DAT E CODE YEAR 1 = 2001 WEEK 35 LINE H
TO-247AC packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
8
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 09/08
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